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How many total SRAM bits will be required to implement a 256KB four-way set associative cache? The cache has 64-byte blocks. Assume that there are 4 extra bits per entry: 1 valid bit, 1 dirty bit, and 2 LRU bits for the replacement policy. Assume that the physical address is 32 bits wide.
Paper#9257470 | Written in 27-Jul-2016Price : $16