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3. Cache Architectures: Associative CachesIn this question you-(Answered)

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3. Cache Architectures: Associative CachesIn this question you will explore the various associative caches. The following is a list ofmemory references given as byte addresses in hexadecimal.0x004, 0x008, 0x00C, 0x010, 0x014, 0x044, 0x048,0x105, 0x04C, 0x050, 0x018, 0x01C, 0x210, 0x020,0x024, 0x018, 0x01C, 0x106, 0x018, 0x01CA block contains 8 words (or 32 bytes).The main memory is 1024 Kbytes (ie. 1024 x 1024 bytes).(a) Main Memory? Determine the number of blocks in main memory.? Determine the minimum number of address bits needed to address each byte in mainmemory.(b) For a direct-mapped cache containing 64 words, organized into eight 8-word blocks. Assume that the cache is initially ?empty?, and that it uses a ?dirty bit?.? Which write strategy is used by this cache?? Show how a 16-bit memory address would be divided into the tag, index, andbyte-offset fields for the direct-mapped cache. Assume byte-addressable memory.? Determine the number data bits stored in this cache.? Determine the total number of bits needed to implement this cache.? Create a table. Identify each memory reference (given above) as either a cache hit or acache miss for the direct-mapped cache.? Show the final contents of the direct-mapped cache.ECE 445 ? Computer Organization 1 of 5 Dr. Craig LorieHomework Assignment #12 Spring 2016(c) Assume you have a 2-way set-associative cache with 8-word blocks and a total size of 64 words which are initially empty. Assume LRU (least recently used) replacement.? Show how a 16-bit memory address would be divided into the tag, index, andbyte-offset fields for the set-associative cache. Assume byte-addressable memory.? Determine the number of data bits stored in this cache.? Determine the total number of bits needed to implement this cache.? Create a table. Identify each memory reference (given above) as either a cache hit or acache miss for the set-associative cache.? Show the final contents of the set-associative cache.(d) Assume you have a fully associative cache with 8 words blocks and a total size of 64 words which are initially empty. Assume LRU replacement.? Show how a 16-bit memory address would be divided into the tag, index, andbyte-offset fields for the set-associative cache. Assume byte-addressable memory.? Determine the number of data bits stored in this cache.? Determine the total number of bits needed to implement this cache.? Create a table. Identify each memory reference (given above) as either a cache hit or acache miss for the fully-associative cache.? Show the final contents of the fully-associative cache.(e) Compare the cache miss rate for the direct-mapped cache, 2-way set-associative cache, and fully associative cache.ECE 445 ? Computer Organization 2 of 5 Dr. Craig LorieHomework Assignment #12 Spring 20164. Cache PerformanceThe table below lists three different cache configurations for a processor with a single level ofcache and their associated miss rates. Assume that the base CPI for the processor is 2.0 and thatthe cache miss penalty, in number of CPU clock cycles, is computed by the following formula:(5 + block size in words) * 10The processor executes a program in which 38% of the instructions contain data references.(a) Determine the effective (or actual) CPI for the three cache configurations.(b) Which cache configuration results in the best processor performance?ECE 445 ? Computer Organization 3 of 5 Dr. Craig LorieHomework Assignment #12 Spring 20165. Cache PerformanceIn the question below: 1 KB is 1024 byte, 1 word is 4 byte, 1 byte is 8 bit, etc.A Processor runs at 2.5 Ghz and has a base CPI=1.8. It executes a program in which 28% ofinstructions contain data references. Below are the specifications of the memory system.(a) Which cache scheme (direct mapped, set associative, fully associative) would you use for level 1 and level 2. Please state a reason. Remember what is most important at each level.(b) Assume that the level 1 cache is direct mapped. Show how a 32-bit byte address would be split into tag, index, etc. for this cache and determine the number of blocks that this cache can store.(c) Assume that the level 2 cache is 4-way set-associative. Show how a 32-bit byte address would be split into tag, index, etc. for this cache and determine the number of blocks that this cache can store and the number of sets that this cache has.(d) What is the effective (or actual) CPI for a processor that has Level-1 cache only?(e) What is the effective CPI for a processor that has both Level-1 and Level-2 caches?(f) How much faster is the processor with 2 cache levels versus 1 cache level?


Homework Assignment #12

 


 

Spring 2016

 


 

Homework #12

 

READING:

 

1. Hennessey & Patterson: 5.1 ? 5.4, 5.7, 5.8

 

PROBLEM SET:

 

1. H/P: problem 5.2, parts 5.2.1 ? 5.2.2

 

2. H/P: problem 5.3, parts 5.3.1 ? 5.3.6

 

3. Cache Architectures: Associative Caches

 

In this question you will explore the various associative caches.

 

memory references given as byte addresses in hexadecimal.

 


 

The following is a list of

 


 

0x004, 0x008, 0x00C, 0x010, 0x014, 0x044, 0x048,

 

0x105, 0x04C, 0x050, 0x018, 0x01C, 0x210, 0x020,

 

0x024, 0x018, 0x01C, 0x106, 0x018, 0x01C

 

A block contains 8 words (or 32 bytes).

 

The main memory is 1024 Kbytes (ie. 1024 x 1024 bytes).

 

(a) Main Memory

 

?

 

?

 


 

Determine the number of blocks in main memory.

 

Determine the minimum number of address bits needed to address each byte in main

 

memory.

 


 

(b) For a direct-mapped cache containing 64 words, organized into eight 8-word blocks.

 

Assume that the cache is initially ?empty?, and that it uses a ?dirty bit?.

 

?

 

?

 

?

 

?

 

?

 

?

 


 

Which write strategy is used by this cache?

 

Show how a 16-bit memory address would be divided into the tag, index, and

 

byte-offset fields for the direct-mapped cache. Assume byte-addressable memory.

 

Determine the number data bits stored in this cache.

 

Determine the total number of bits needed to implement this cache.

 

Create a table. Identify each memory reference (given above) as either a cache hit or a

 

cache miss for the direct-mapped cache.

 

Show the final contents of the direct-mapped cache.

 


 

ECE 445 ? Computer Organization

 


 

1 of 5

 


 

Dr. Craig Lorie

 


 

Homework Assignment #12

 


 

Spring 2016

 


 

(c) Assume you have a 2-way set-associative cache with 8-word blocks and a total size

 

of 64 words which are initially empty. Assume LRU (least recently used) replacement.

 

?

 

?

 

?

 

?

 

?

 


 

Show how a 16-bit memory address would be divided into the tag, index, and

 

byte-offset fields for the set-associative cache. Assume byte-addressable memory.

 

Determine the number of data bits stored in this cache.

 

Determine the total number of bits needed to implement this cache.

 

Create a table. Identify each memory reference (given above) as either a cache hit or a

 

cache miss for the set-associative cache.

 

Show the final contents of the set-associative cache.

 


 

(d) Assume you have a fully associative cache with 8 words blocks and a total size

 

of 64 words which are initially empty. Assume LRU replacement.

 

?

 

?

 

?

 

?

 

?

 


 

Show how a 16-bit memory address would be divided into the tag, index, and

 

byte-offset fields for the set-associative cache. Assume byte-addressable memory.

 

Determine the number of data bits stored in this cache.

 

Determine the total number of bits needed to implement this cache.

 

Create a table. Identify each memory reference (given above) as either a cache hit or a

 

cache miss for the fully-associative cache.

 

Show the final contents of the fully-associative cache.

 


 

(e) Compare the cache miss rate for the direct-mapped cache, 2-way set-associative cache,

 

and fully associative cache.

 


 

ECE 445 ? Computer Organization

 


 

2 of 5

 


 

Dr. Craig Lorie

 


 

Homework Assignment #12

 


 

Spring 2016

 


 

4. Cache Performance

 

The table below lists three different cache configurations for a processor with a single level of

 

cache and their associated miss rates. Assume that the base CPI for the processor is 2.0 and that

 

the cache miss penalty, in number of CPU clock cycles, is computed by the following formula:

 

(5 + block size in words) * 10

 

The processor executes a program in which 38% of the instructions contain data references.

 

(a) Determine the effective (or actual) CPI for the three cache configurations.

 

(b) Which cache configuration results in the best processor performance?

 


 

ECE 445 ? Computer Organization

 


 

3 of 5

 


 

Dr. Craig Lorie

 


 

Homework Assignment #12

 


 

Spring 2016

 


 

5. Cache Performance

 

In the question below: 1 KB is 1024 byte, 1 word is 4 byte, 1 byte is 8 bit, etc.

 

A Processor runs at 2.5 Ghz and has a base CPI=1.8. It executes a program in which 28% of

 

instructions contain data references. Below are the specifications of the memory system.

 


 

(a) Which cache scheme (direct mapped, set associative, fully associative) would you use for

 

level 1 and level 2. Please state a reason. Remember what is most important at each level.

 

(b) Assume that the level 1 cache is direct mapped. Show how a 32-bit byte address would

 

be split into tag, index, etc. for this cache and determine the number of blocks that this

 

cache can store.

 

(c) Assume that the level 2 cache is 4-way set-associative. Show how a 32-bit byte address

 

would be split into tag, index, etc. for this cache and determine the number of blocks that

 

this cache can store and the number of sets that this cache has.

 

(d) What is the effective (or actual) CPI for a processor that has Level-1 cache only?

 

(e) What is the effective CPI for a processor that has both Level-1 and Level-2 caches?

 

(f) How much faster is the processor with 2 cache levels versus 1 cache level?

 


 

ECE 445 ? Computer Organization

 


 

4 of 5

 


 

Dr. Craig Lorie

 


 

Homework Assignment #12

 


 

Spring 2016

 


 

6. Virtual Memory

 


 

ECE 445 ? Computer Organization

 


 

5 of 5

 


 

Dr. Craig Lorie

 


 

 

Paper#9209722 | Written in 27-Jul-2016

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