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##### This question will be due on 5/10/16 and this about exercise-(Answered)

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This question will be due on 5/10/16 and this about exercise

ET1220: Module 4 Basic Sequential Logic and Registers

Exercise 4.1

Latches, Flip-Flops, Timers, and Shift Registers

1. If the waveforms in the figure below are applied to an active-HIGH S-R Latch, draw the resulting Q

output waveform in relation to the inputs.

2. For a gated S-R latch, determine the Q and ? outputs for the inputs in the figure below. Show them

in proper relation to the enable input. Assume that Q starts LOW.

3. Two edge-triggered D flip-flops are shown in the figure below. If the inputs are as shown, draw the

Q output of each flip-flop relative to the clock and explain the difference between the two. The flipflops are initially RESET.

4. For a positive edge-triggered J-K flip-flop with inputs as shown in the figure below, determine the Q

output relative to the clock. Assume that Q starts LOW.

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ET1220: Module 4 Basic Sequential Logic and Registers

Exercise 4.1

Latches, Flip-Flops, Timers, and Shift Registers

5. Determine the Q waveform relative to the clock if the signals shown in the figure below are applied

to the inputs of the J-K flip-flop. Assume that Q is initially LOW.

6. For the circuit in the figure below, develop a timing diagram for 8 clock pulses, showing the QA and

QB outputs in relation to the clock.

7. Typically, a manufacturer?s datasheet specifies four different propagation delay times associated

with a flip-flop. Name and describe each one.

8. An output pulse of 5 ?s duration is to be generated by a 555 operating as a one-shot. Using a

capacitor of 10,000 pF, determine the value of external resistance required.

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ET1220: Module 4 Basic Sequential Logic and Registers

Exercise 4.1

Latches, Flip-Flops, Timers, and Shift Registers

9. What would be the state of shift register C in the figure below after 2 correct code digits are entered

for the entry code 4739?

10. What is the storage capacity of a register that can retain 2 bytes of data?

11. The sequence 1011 is applied to the input of a 4-bit serial shift register that is initially cleared. What

would be the state of the shift register after 3 clock pulses?

12. For the serial in/ serial out shift register, determine the data-output waveform for the data- input

and clock waveforms in the figure below. Assume that the register is initially cleared.

13. The shift register in the part (a) of the figure below has SHIFT/???????? and CLK inputs, as shown in

part (b). The serial data input (SER) is a 0. The parallel data inputs are D0 = 1, D1 = 0, D2 = 1, and D3 =

0, as shown. Develop the data-output waveform in relation to the inputs.

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ET1220: Module 4 Basic Sequential Logic and Registers

Exercise 4.1

Latches, Flip-Flops, Timers, and Shift Registers

14. Based on the waveforms in part (a) of the figure below, determine the problem with the register in

part (b) of the figure.

Submission Requirements:

Submit your answers in a Microsoft Word document. The submission should use:

Font: Arial; 12-point

Line spacing: Double

Evaluation Criteria:

Your submission will be evaluated against the following criteria:

Did you include appropriate steps or rationale to determine the answers to questions wherever

required?

Did you correctly answer each question?

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Paper#9209532 | Written in 27-Jul-2016

Price : \$22